The present invention generally relates to voltage level setting circuits, and more particularly to a voltage level setting circuit for setting in a signal processing circuit system a voltage level of a reference portion of an input signal which is obtained from a signal source circuit system.
FIG. 1 shows an example of an image signal processing circuit employing the conventional voltage level setting circuit. An image signal from a signal source circuit system (not shown) is applied to a terminal 10 and is supplied to an image signal processing circuit system 11 through a coupling capacitor C1. The image signal processing circuit system 11 comprises an amplifier 12 for amplifying the incoming image signal from the coupling capacitor C1, an analog-to-digital (A/D) converter 13 for converting an output signal of the amplifier 12 into a digital signal, a digital signal processing circuit 14 for subjecting the digital signal from the A/D converter 13 to a signal processing including a luminance correction and the like, and a voltage level setting circuit 15. The amplifier 12, the A/D converter 13 and the digital signal processing circuit 14 constitute a signal processing circuit. An output digital signal of the image signal processing circuit system 11 is supplied to a circuit system (not shown) in a subsequent stage through a terminal 16.
When the voltage level of the image signal is within a voltage level range which can be processed in the image signal processing circuit system 11, there is no need to provide the coupling capacitor C1 nor the voltage level setting circuit 15. However, the voltage level of the image signal generally does not always fall within the voltage level range which can be processed in the image signal processing circuit system 11.
For example, it will be assumed for convenience, sake that the image signal is obtained from a charge coupled device (CCD) of the signal source circuit system. In this case, the voltage level of the image signal is 6 V to 7 V, but a reference voltage level of a reference portion of the image signal can be converted by use of the coupling capacitor C1 and the voltage level setting circuit 15. The reference voltage is used as a reference level of the input signal. For this reason, the voltage level of the image signal can be converted so as to fall within the voltage level range which can be processed in the image signal processing circuit system 11, such as to a voltage level range of 2 V to 4 V, for example.
FIG. 2 is a circuit diagram for explaining the operation of a first example of the voltage level setting circuit 15. In FIG. 2, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. The image signal from a signal source 17 such as the CCD is applied to the terminal 10. A voltage level setting circuit 15a comprises a bias resistor R1 and a bias voltage source for supplying a bias voltage V.sub.B.
When the image signal from the signal source 17 has a voltage level V1 as shown in FIG. 3(A) made up of a D.C. component indicated by a phantom line and an A.C. component, this image signal has a voltage level V2 shown in FIG. 3(B) after it passes through the coupling capacitor C1. In other words, it is possible to set a reference voltage level of the image signal (V2) to the bias voltage V.sub.B.
However, according to the voltage level setting circuit 15a, a signal component having a frequency lower than a frequency determined by the coupling capacitor C1 and the bias resistor R1 becomes attenuated. For example, a D.C. step shown in FIG. 3(A) becomes attenuated exponentially (by e.sup.-t/C1R1, where t denotes the time) as indicated by a phantom line in FIG. 3(B). For this reason, there is a problem in that an appropriate signal transmission cannot be carried out for the D.C. signal component and the low-frequency signal component having a time constant greater than the time constant determined by the coupling capacitor C1 and the resistor R1.
FIG. 4 is a circuit diagram for explaining the operation of a second example of the voltage level setting circuit 15. In FIG. 4, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted. A voltage level setting circuit 15b comprises a switching circuit S1 and a bias voltage source for supplying the bias voltage V.sub.b.
The image signal from the signal source 17 has a voltage level V3 as shown in FIG. 5(A), for example, and the switching circuit S1 is turned ON while the image signal (V3) has a reference voltage level a during the predetermined time period. Hence, this image signal has a voltage level V4 shown in FIG. 5(B) after it passes through the coupling capacitor C1 and the reference voltage level is clamped to the bias voltage V.sub.B. On the other hand, the switching circuit S1 is turned OFF while a picture information portion b of the image signal (V3) is received at the terminal 10, and a D.C. voltage part of the picture information portion b is clamped.
The voltage level setting circuit 15b forcibly sets the voltage level of the image signal to the bias voltage V.sub.B during the predetermined time period corresponding to the reference portion of the image signal. Since this forced setting of the voltage level must be carried out instantaneously, there is a need to carry out a charge and discharge operation at a high speed. Hence, the switching circuit S1 is generally constituted by a semiconductor element such as metal oxide semiconductor (MOS) element and a bipolar element through which a relatively large current may flow. But when the semiconductor element is used to constitute the switching circuit S1, a clock signal feedthrough occurs thereby generating an offset voltage .DELTA.V shown in FIG. 5(B). This clock signal feedthrough occurs because a charge is generated at a channel of the MOS element (transistor) when the MOS element is turned ON and this charge affects the voltages V4 and V.sub.B when the MOS element is turned OFF. Furthermore, it is difficult to maintain the bias voltage V.sub.B stable when the relatively large current flows through the switching circuit S1. Therefore, there is a problem in that an appropriate signal transmission cannot be carried out.